«Implicit Mixed-Mode Simulation of VLSI Circuits by Albert Tatum Davis Submitted in Partial Fulﬁllment of the Requirements for the Degree Doctor of ...»
Implicit Mixed-Mode Simulation
of VLSI Circuits
Albert Tatum Davis
Submitted in Partial Fulﬁllment
Requirements for the Degree
Doctor of Philosophy
Supervised by Robert J. Bowman
Department of Electrical Engineering
College of Engineering and Applied Science
University of Rochester
Rochester, New York
Albert Davis was born on June 29, 1950 in Albany, New York. He
graduated from Clarkson College in 1972 with a B.S. degree in Electrical and Computer engineering, with a specialty in communications and circuit theory.
From 1972 to 1978 he was employed as an analog circuit designer, working primarily in the audio industry. In 1978, he founded Tatum Labs, a consulting ﬁrm, to do analog circuit design. Beginning in 1980, his work became primarily software tools for circuit designers. Tatum Labs developed and marketed entry level CAD software, including a circuit simulator, for board level circuits. He sold Tatum Labs in 1986 to pursue full time graduate study.
In 1984, he enrolled in a part time Masters program at the University of Bridgeport. He received the M.S. degree in 1986. In 1986 he enrolled in a Ph.D. program at Clarkson University. In 1987, he transferred to the University of Rochester to complete his research under Dr. Robert Bowman. His research concentrated on simulation of mixed analog and digital circuits.
ii Abstract Circuit simulation is an important tool for the design and veriﬁcation of integrated circuits. It is increasingly common to combine analog and digital subcircuits on a single chip. These combined circuits present problems for simulation.
In this dissertation some techniques are presented to combine diﬀerent simulation modes, logic and analog, implicitly, without direct instructions from the user.
This results in improved simulation of combined analog and digital circuits.
A uniﬁed data structure allows the free mixing of analog and digital devices, with support for both analog and logic level simulation simultaneously. The analog simulation is based on traditional algorithms, LU decomposition by a modiﬁed Crout method and iteration by Newton’s method, enhanced to support incremental changes to the matrix and to bypass of parts of the matrix solution that are inactive or already converged. The resulting simulation is much faster than the traditional solution method with bypass only applied to model evaluation, without loss of accuracy. The logic level simulation is based on traditional event driven logic simulation, where logic states are propagated. A logicelement has both a circuit and logic description.
A method is presented to automatically choose between logic and analog simulation in parts of the circuit that have a logic level description. The choice is based on the assumption that when the digital signals appear to be clean a digital simulation is valid. When the digital signals show race and spike conditions or slow transitions they are suspect and analog simulation is used for the problem parts of the circuit. When the conversion between modes is poorly deﬁned or diﬃcult to make the analog mode is selected. The simulation mode changes dynamically as the simulation runs. Mode changes can be made on parts of the circuit as small as a single gate.
For digital circuits these techniques are much faster than full analog simulation.
They accurately simulate cases where digital simulation fails by applying analog techniques on a local basis and they simulate the interface between analog and digital parts of the circuit better than other methods.
I would like to thank Mike Wengler, Vassilios Tourassis, and Rob Fowler for serving on my thesis committee. I am particularly grateful to Rob Fowler for help with the dissertation, and VT for bringing up the right points at committee meetings.
I thank my thesis adviser, Robert Bowman, for maintaining faith, even when I lost it, no matter how rough things were.
I acknowledge the ﬁnancial support of Siemens Corporation, and Analog Devices Corporation. I also thank Tatum Labs for the use of the “ECA-2” source code, to use as a base for the “URECA” simulator, and for providing some extra income in the form of ECA-2 royalties, so I was a little better oﬀ ﬁnancially than most graduate students.
I thank Ken Ebert for buying my business (Tatum Labs) so I could pursue graduate study, full time.
I thank Professors Gaylord Northrup and Gerry Volpe at Bridgeport for the many fruitful conversations that inspired me to go on for doctoral studies.
Since life is not complete without recreation, I thank the Rochester Bicycling Club, especially Ann Carroll and Jean Jaslow, for helping me maintain my sanity by providing an escape when the pressure was too much.
Finally, I thank my parents, Albert and Marian, for everything.
As technology improves, integrated circuits grow in size and complexity. Such circuit complexity precludes the use of breadboarding for prototyping, and demands computer-assisted analysis oﬀered by simulation. The size and complexity of circuits has grown to the point where, often, circuit simulation has become the major cost in the development cycle. In many cases, however, a simulation does not produce satisfactory results. Changes to the circuit description are required to get the simulator to run. Often, the resulting model or topology may no longer be an accurate representation of the actual circuit. A circuit may often be simulated successfully by partitioning into smaller blocks and applying diﬀerent algorithms to diﬀerent blocks. Reconnecting the blocks together often causes interactions that separate simulations do not show.
Considerable progress in simulation has been made for digital circuits, and for
many classes of analog circuits. However, there are classes of circuits, particularly in the analog domain, that continue to plague simulation tools with problems of convergence and accuracy. These circuits are characterized by widely varying time constants, and often include mixed analog and digital blocks with feedback. They can be small or large. The number of active elements ranges from 5 to 100,000 devices. Examples of the problem circuits include A/D converters, phase locked loops, switched capacitor circuits, and oscillator start-up circuits.
A new generation of mixed-mode simulators has evolved to apply diﬀerent algorithms to diﬀerent blocks. However, the burden of selecting the most appropriate algorithm for each block rests with the designer. The netlist accepts both circuit and logic level elements, with some restrictions on how they connect together. Some require entire subcircuit blocks to be all either digital or analog, but not mixed. Existing simulators use this information to explicitly partition the circuit into analog and digital parts, then apply the nominally appropriate algorithm to each part, with explicit conversions at the interfaces.
At ﬁrst this may seem to not be a problem, since the designer knows how the circuit blocks should work, but too often the assumptions the designer made do not hold. Only a more detailed simulation would show the failings of the circuit. The information required to select the simulation algorithm is often the very information the designer is seeking from the simulation.
Some circuits, speciﬁed on a device level, are best simulated by traditional
Some are best done by a combination. Likewise, some circuits, speciﬁed in logic level, can be accurately simulated by traditional logic level simulation. Some require a more accurate “timing” simulation, which is the same as relaxation based analog simulation, to properly simulate race conditions, or other improper signals.
The two levels to consider in mixed-mode simulation are actually circuit and behavioral. Behavioral modeling is simply evaluating the function performed by a block, and using the result. Circuit level means to evaluate the components that make up a block, and how they interact. Evaluating each component can be either circuit level or behavioral. Signals can also be considered to be either circuit level or behavioral. Circuit level signals can be measured using instruments.
Behavioral level signals are
quantities, or interpretations or circuit level signals. With this in mind, the decision process is whether to use the concrete (circuit level) or abstract (behavioral level).
In the behavioral level, only the apparent behavior at the terminals is considered, but this is not always good enough. Some means is necessary to determine whether it is necessary to simulate the internal behavior of blocks, instead of relying on their nominal behavior. Given a circuit block, the behavior is con
simulation runs, and dynamically switch modes locally. Assuming the behavioral mode is logic level, various acceleration techniques are available, including the use of an event queue to avoid computer time when there is no action. This research investigates eﬃcient techniques for mixing this with traditional analog simulation.
The following areas were investigated in this work. The results of this research were incorporated into a general purpose simulator, “URECA”.
Multiple solution methods Some circuits are best solved by traditional methods (Newton-Raphson, LU decomposition, etc.) Some are best solved by other methods, such as relaxation, harmonic balance, event driven, etc.
Three methods were chosen here: traditional (Newton’s method, LU decomposition), relaxation, and gate level (behavioral, with discrete states).
Automatic choice of method Simulators exist that use a variety of methods.
All known simulators that can use more than one method require the user to partition the circuit and specify what method to use where. In this work, the choice between the three methods named above is made implicitly, for each device, at run time. The choice of method changes as the simulation
Heuristic shortcuts Often, it is not necessary to do all calculations, or use the most complete model. Research was done to determine what shortcuts can be taken, and how to make these decisions automatically.
the circuit. It may be advantageous to apply diﬀerent methods to diﬀerent parts of the circuit. Varying time constants could allow more economic solution if the slow parts can be simulated with a larger step size. There exist known methods of partitioning, but they are slow. (Time grows superlinearly with circuit size.) Likewise, the time needed to order the equations (pivoting) grows superlinearly with circuit size. In this work, ordering and partitioning is done crudely as part of subcircuit expansion, resulting in a bordered block diagonal matrix. Partitioning is implicit. Simulation methods are applied to each device as appropriate. Partial solution of the matrix uses a trace of how changes propagate to determine the parts to operate on.
Partitioning is implicit, and can change dynamically.
Chapter 2 Background of Circuit Simulation
2.1 Types of Simulation This section introduces several types of simulation, with a brief overview. More detail is available in sections 2.2 and 2.4. Descriptions of some of the programs are in section 2.3.
2.1.1 Classical network simulation The common conventional circuit simulators are based on a mechanization of the methods taught as undergraduate circuit theory. The most common (SPICE) are based on modiﬁed nodal analysis. Nodal analysis is simply the application of Kirchoﬀ’s current law. This results in a singular matrix if there are ideal voltage sources, so a modiﬁed nodal analysis adds equations for the currents
The resulting system of linear equations is solved by LU decomposition, and forward and back substitution. Without sparse matrix techniques, the running time for this is O(n3 ). Further details on this are available in any text on numerical analysis.